%0 Conference Paper %1 conf/fmcad/SubramanyanVRM15 %A Subramanyan, Pramod %A Vizel, Yakir %A Ray, Sayak %A Malik, Sharad %B FMCAD %D 2015 %E Kaivola, Roope %E Wahl, Thomas %I IEEE %K dblp %P 160-167 %T Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. %U http://dblp.uni-trier.de/db/conf/fmcad/fmcad2015.html#SubramanyanVRM15 %@ 978-0-9835-6785-1

@inproceedings{conf/fmcad/SubramanyanVRM15, added-at = {2023-09-30T00:00:00.000+0200}, author = {Subramanyan, Pramod and Vizel, Yakir and Ray, Sayak and Malik, Sharad}, biburl = {https://www.bibsonomy.org/bibtex/2ba5bde4c5eee27821064d2016dae5525/dblp}, booktitle = {FMCAD}, crossref = {conf/fmcad/2015}, editor = {Kaivola, Roope and Wahl, Thomas}, ee = {https://doi.org/10.1109/FMCAD.2015.7542266}, interhash = {28bf4c19c1a5d60de3fed51388673130}, intrahash = {ba5bde4c5eee27821064d2016dae5525}, isbn = {978-0-9835-6785-1}, keywords = {dblp}, pages = {160-167}, publisher = {IEEE}, timestamp = {2024-04-09T23:58:44.000+0200}, title = {Template-based Synthesis of Instruction-Level Abstractions for SoC Verification.}, url = {http://dblp.uni-trier.de/db/conf/fmcad/fmcad2015.html#SubramanyanVRM15}, year = 2015 }