%0 Conference Paper %1 conf/isvlsi/HerathPKS18 %A Herath, Kalindu %A Prakash, Alok %A Kanewala, Udaree %A Srikanthan, Thambipillai %B ISVLSI %D 2018 %I IEEE Computer Society %K dblp %P 209-214 %T Communication-Aware Module Placement for Power Reduction in Large FPGA Designs. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2018.html#HerathPKS18 %@ 978-1-5386-7099-6

@inproceedings{conf/isvlsi/HerathPKS18, added-at = {2023-03-24T00:00:00.000+0100}, author = {Herath, Kalindu and Prakash, Alok and Kanewala, Udaree and Srikanthan, Thambipillai}, biburl = {https://www.bibsonomy.org/bibtex/2d9dbfa616f67050224dbfc2af568b243/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2018}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2018.00047}, interhash = {2da938bd454d8e016a5594f69e5a4d51}, intrahash = {d9dbfa616f67050224dbfc2af568b243}, isbn = {978-1-5386-7099-6}, keywords = {dblp}, pages = {209-214}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:08:32.000+0200}, title = {Communication-Aware Module Placement for Power Reduction in Large FPGA Designs.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2018.html#HerathPKS18}, year = 2018 }