%0 Conference Paper %1 conf/vlsid/YangWVXW05 %A Yang, Shengqi %A Wolf, Wayne H. %A Vijaykrishnan, Narayanan %A Xie, Yuan %A Wang, Wenping %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 165-170 %T Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#YangWVXW05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/YangWVXW05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Yang, Shengqi and Wolf, Wayne H. and Vijaykrishnan, Narayanan and Xie, Yuan and Wang, Wenping}, biburl = {https://www.bibsonomy.org/bibtex/2c0199beedf070682b12a188868759dd8/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.41}, interhash = {2dc13074262171b6d78ad0863c66dd39}, intrahash = {c0199beedf070682b12a188868759dd8}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {165-170}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:41.000+0200}, title = {Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#YangWVXW05}, year = 2005 }