%0 Conference Paper %1 conf/vlsid/PandeyKSG14 %A Pandey, Jai Gopal %A Karmakar, Arindam %A Shekhar, Chandra %A Gurunarayanan, S. %B VLSID %D 2014 %I IEEE Computer Society %K dblp %P 300-305 %T A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2014.html#PandeyKSG14 %@ 978-1-4799-2513-1

@inproceedings{conf/vlsid/PandeyKSG14, added-at = {2023-03-24T00:00:00.000+0100}, author = {Pandey, Jai Gopal and Karmakar, Arindam and Shekhar, Chandra and Gurunarayanan, S.}, biburl = {https://www.bibsonomy.org/bibtex/2cab1d7cac1dc19151554959b8f16a99b/dblp}, booktitle = {VLSID}, crossref = {conf/vlsid/2014}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2014.58}, interhash = {31fe82a484ee313299c3d692bbc2a2ff}, intrahash = {cab1d7cac1dc19151554959b8f16a99b}, isbn = {978-1-4799-2513-1}, keywords = {dblp}, pages = {300-305}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:04:47.000+0200}, title = {A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2014.html#PandeyKSG14}, year = 2014 }