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Disambiguation of "Pandey, Jai Gopal"

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A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm.

, , , and . VLSID, page 300-305. IEEE Computer Society, (2014)

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Shantanu Pandey

Karappurath Gopalan

Kreshna Gopal

Gopal Mamdapurkar

Dharmendra Pandey

 

Other publications of authors with the same name

Architectures and algorithms for image and video processing using FPGA-based platform., , and . VDAT, page 1. IEEE, (2014)Hardware architectures for PRESENT block cipher and their FPGA implementations., , and . IET Circuits Devices Syst., 13 (7): 958-969 (2019)SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking., , , , , and . VLSID, page 547-552. IEEE, (2024)GIFT cipher usage in image data security: hardware implementations, performance and statistical analyses., and . J. Real Time Image Process., 18 (6): 2551-2567 (2021)An RNS Implementation of the Elliptic Curve Cryptography for IoT Security., , and . TPS-ISA, page 66-72. IEEE, (2019)A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher., , and . VLSID, page 392-397. IEEE Computer Society, (2018)Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends., , , and . Comput. Secur., (June 2023)Dual-Edge Triggered Lightweight Implementation of AES for IoT Security., , , , , and . VDAT, volume 1066 of Communications in Computer and Information Science, page 298-307. Springer, (2019)An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation., , and . VDAT, volume 711 of Communications in Computer and Information Science, page 270-278. Springer, (2017)A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs., , , , , and . SoCC, page 96-101. IEEE, (2018)