%0 Conference Paper %1 conf/iscas/ZhangZC13 %A Zhang, Yaojun %A Zhang, Lu %A Chen, Yiran %B ISCAS %D 2013 %I IEEE %K dblp %P 113-116 %T MLC STT-RAM design considering probabilistic and asymmetric MTJ switching. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2013.html#ZhangZC13 %@ 978-1-4673-5760-9

@inproceedings{conf/iscas/ZhangZC13, added-at = {2022-07-04T00:00:00.000+0200}, author = {Zhang, Yaojun and Zhang, Lu and Chen, Yiran}, biburl = {https://www.bibsonomy.org/bibtex/2d080523e966070fcb21a98f3845f4144/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2013}, ee = {https://doi.org/10.1109/ISCAS.2013.6571795}, interhash = {3ebf93d21857f8e750358d2d48252c9c}, intrahash = {d080523e966070fcb21a98f3845f4144}, isbn = {978-1-4673-5760-9}, keywords = {dblp}, pages = {113-116}, publisher = {IEEE}, timestamp = {2024-04-10T17:47:08.000+0200}, title = {MLC STT-RAM design considering probabilistic and asymmetric MTJ switching.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2013.html#ZhangZC13}, year = 2013 }