%0 Journal Article %1 journals/vlsisp/TrenasLZA02 %A Trenas, María A. %A López, Juan %A Zapata, Emilio L. %A Argüello, Francisco %D 2002 %J VLSI Signal Processing %K dblp %N 3 %P 255-273 %T A Configurable Architecture for the Wavelet Packet Transform. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp32.html#TrenasLZA02 %V 32

@article{journals/vlsisp/TrenasLZA02, added-at = {2008-07-22T00:00:00.000+0200}, author = {Trenas, María A. and López, Juan and Zapata, Emilio L. and Argüello, Francisco}, biburl = {https://www.bibsonomy.org/bibtex/2fe4bec483ec4a0c13dc4c683bf352c04/dblp}, date = {2008-07-22}, description = {dblp}, ee = {http://dx.doi.org/10.1023/A:1020221003822}, interhash = {48b34e9297f3ef268d53d55f74a18773}, intrahash = {fe4bec483ec4a0c13dc4c683bf352c04}, journal = {VLSI Signal Processing}, keywords = {dblp}, number = 3, pages = {255-273}, timestamp = {2008-07-23T11:59:50.000+0200}, title = {A Configurable Architecture for the Wavelet Packet Transform.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp32.html#TrenasLZA02}, volume = 32, year = 2002 }