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A Configurable Architecture for the Wavelet Packet Transform.

, , , and . VLSI Signal Processing, 32 (3): 255-273 (2002)

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Parallelization Strategies for the VMEC Program., , , and . PARA, volume 1541 of Lecture Notes in Computer Science, page 483-490. Springer, (1998)Unified Locality-Sensitive Signatures for Transactional Memory., , , and . Euro-Par (1), volume 6852 of Lecture Notes in Computer Science, page 326-337. Springer, (2011)SAD computation based on online arithmetic for motion estimation., , , , and . Microprocess. Microsystems, 30 (5): 250-258 (2006)Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA., , , , and . FPL, page 1-4. IEEE, (2006)A compiler tool to predict memory hierarchy performance of scientific codes., , , and . Parallel Comput., 30 (2): 225-248 (2004)Efficient Data Structure and Highly Scalable Algorithm for Total-Viewshed Computation., , , and . IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 8 (1): 304-310 (2015)On Automatic Parallelization of Irregular Reductions on Scalable Shared Memory Systems., , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 422-429. Springer, (1999)Parallel algorithm for principal components based on Hotelling's iterative procedure., , and . PDP, page 144-149. IEEE, (1993)A VLSI systolic architecture for fuzzy clustering., , , and . Microprocess. Microprogramming, 24 (1-5): 647-654 (1988)A DBT-based VLSI systolic architecture for hard squared error clustering., , and . Microprocessing and Microprogramming, 27 (1-5): 299-305 (1989)