%0 Conference Paper %1 conf/aspdac/MiuraKK04 %A Miura, Noriyuki %A Kato, Naoki %A Kuroda, Tadahiro %B ASP-DAC %D 2004 %E Imai, Masaharu %I IEEE Computer Society %K dblp %P 434-437 %T Practical methodology of post-layout gate sizing for 15% more power saving. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2004.html#MiuraKK04 %@ 0-7803-8175-0

@inproceedings{conf/aspdac/MiuraKK04, added-at = {2023-03-23T00:00:00.000+0100}, author = {Miura, Noriyuki and Kato, Naoki and Kuroda, Tadahiro}, biburl = {https://www.bibsonomy.org/bibtex/2e3d5a20e27a23da33021c68aa045b373/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2004}, editor = {Imai, Masaharu}, ee = {https://dl.acm.org/citation.cfm?id=1015199}, interhash = {4ddbec01599595c70ad49cff815c35d0}, intrahash = {e3d5a20e27a23da33021c68aa045b373}, isbn = {0-7803-8175-0}, keywords = {dblp}, pages = {434-437}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:15:59.000+0200}, title = {Practical methodology of post-layout gate sizing for 15% more power saving.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2004.html#MiuraKK04}, year = 2004 }