%0 Journal Article %1 journals/jssc/KimOCSSMLR13 %A Kim, Hyung Seok %A Ornelas, Carlos %A Chandrashekar, Kailash %A Shi, Dan %A en Su, Pin %A Madoglio, Paolo %A Li, Yee William %A Ravi, Ashoke %D 2013 %J IEEE J. Solid State Circuits %K dblp %N 7 %P 1721-1729 %T A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. %U http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#KimOCSSMLR13 %V 48

@article{journals/jssc/KimOCSSMLR13, added-at = {2020-08-30T00:00:00.000+0200}, author = {Kim, Hyung Seok and Ornelas, Carlos and Chandrashekar, Kailash and Shi, Dan and en Su, Pin and Madoglio, Paolo and Li, Yee William and Ravi, Ashoke}, biburl = {https://www.bibsonomy.org/bibtex/24d37cbcbed7c88d3770afb89127bae49/dblp}, ee = {https://doi.org/10.1109/JSSC.2013.2253407}, interhash = {56f020f446429232275b57c9e6cd7741}, intrahash = {4d37cbcbed7c88d3770afb89127bae49}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 7, pages = {1721-1729}, timestamp = {2020-08-31T11:41:29.000+0200}, title = {A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#KimOCSSMLR13}, volume = 48, year = 2013 }