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Disambiguation of "Madoglio, Paolo"

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A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.

, , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1721-1729 (2013)

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Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Pesaresi

 

Other publications of authors with the same name

Quantization Effects in All-Digital Phase-Locked Loops., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (12): 1120-1124 (2007)Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS., , , , , and . ISCAS, page 1-4. IEEE, (2020)A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC., , , , , , and . ESSCIRC, page 193-196. IEEE, (2012)AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic., , , , , and . EURASIP J. Embed. Syst., (2010)A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving., , , , , , and . IEEE J. Solid State Circuits, 45 (7): 1410-1420 (2010)A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 168-170. IEEE, (2012)A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS., , and . IEEE J. Solid State Circuits, 44 (12): 3422-3433 (2009)A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving., , , , , , and . ESSCIRC, page 152-155. IEEE, (2009)A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique., , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1721-1729 (2013)A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 47 (12): 3184-3196 (2012)