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%0 Journal Article
%1 journals/tvlsi/RatkovicPSUCV18
%A Ratkovic, Ivan
%A Palomar, Oscar
%A Stanic, Milan
%A Unsal, Osman Sabri
%A Cristal, Adrián
%A Valero, Mateo
%D 2018
%J IEEE Trans. Very Large Scale Integr. Syst.
%K dblp
%N 4
%P 639-652
%T Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
%U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#RatkovicPSUCV18
%V 26
@article{journals/tvlsi/RatkovicPSUCV18,
added-at = {2022-06-23T00:00:00.000+0200},
author = {Ratkovic, Ivan and Palomar, Oscar and Stanic, Milan and Unsal, Osman Sabri and Cristal, Adrián and Valero, Mateo},
biburl = {https://www.bibsonomy.org/bibtex/23d96ce288fd6ffc65df2114c8c70c499/dblp},
ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2784807},
interhash = {5ea924e1ddbc0a8c5599418039f9e0e4},
intrahash = {3d96ce288fd6ffc65df2114c8c70c499},
journal = {IEEE Trans. Very Large Scale Integr. Syst.},
keywords = {dblp},
number = 4,
pages = {639-652},
timestamp = {2024-04-08T14:31:39.000+0200},
title = {Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#RatkovicPSUCV18},
volume = 26,
year = 2018
}
