13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Please log in to take part in the discussion (add own reviews or comments).
Cite this publication
More citation styles
- please select -
%0 Conference Paper
%1 conf/isscc/HirairiOFYTNSS12
%A Hirairi, Koji
%A Okuma, Yasuyuki
%A Fuketa, Hiroshi
%A Yasufuku, Tadashi
%A Takamiya, Makoto
%A Nomura, Masahiro
%A Shinohara, Hirofumi
%A Sakurai, Takayasu
%B ISSCC
%D 2012
%I IEEE
%K dblp
%P 486-488
%T 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2012.html#HirairiOFYTNSS12
%@ 978-1-4673-0376-7
@inproceedings{conf/isscc/HirairiOFYTNSS12,
added-at = {2012-04-18T00:00:00.000+0200},
author = {Hirairi, Koji and Okuma, Yasuyuki and Fuketa, Hiroshi and Yasufuku, Tadashi and Takamiya, Makoto and Nomura, Masahiro and Shinohara, Hirofumi and Sakurai, Takayasu},
biburl = {https://www.bibsonomy.org/bibtex/2f400a38f0a103f77b01887f47afc92e1/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2012},
ee = {http://dx.doi.org/10.1109/ISSCC.2012.6177102},
interhash = {61c8783237f3d0ce6a371a9162fb92c3},
intrahash = {f400a38f0a103f77b01887f47afc92e1},
isbn = {978-1-4673-0376-7},
keywords = {dblp},
pages = {486-488},
publisher = {IEEE},
timestamp = {2012-04-19T11:43:30.000+0200},
title = {13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2012.html#HirairiOFYTNSS12},
year = 2012
}
