%0 Conference Paper %1 conf/pimrc/CanetVAVL04 %A Canet, Ma José %A Vicedo, Felip %A Almenar, Vicenç %A Valls, Javier %A de Lima, Eduardo R. %B PIMRC %D 2004 %I IEEE %K dblp %P 531-535 %T A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. %U http://dblp.uni-trier.de/db/conf/pimrc/pimrc2004.html#CanetVAVL04

@inproceedings{conf/pimrc/CanetVAVL04, added-at = {2017-07-12T00:00:00.000+0200}, author = {Canet, Ma José and Vicedo, Felip and Almenar, Vicenç and Valls, Javier and de Lima, Eduardo R.}, biburl = {https://www.bibsonomy.org/bibtex/29ff185608d4010626ba97327aca3ff66/dblp}, booktitle = {PIMRC}, crossref = {conf/pimrc/2004}, ee = {https://doi.org/10.1109/PIMRC.2004.1370927}, interhash = {625481eb182b110da9aad14909a2b779}, intrahash = {9ff185608d4010626ba97327aca3ff66}, keywords = {dblp}, pages = {531-535}, publisher = {IEEE}, timestamp = {2017-07-13T12:14:58.000+0200}, title = {A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems.}, url = {http://dblp.uni-trier.de/db/conf/pimrc/pimrc2004.html#CanetVAVL04}, year = 2004 }