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Disambiguation of "Canet, Ma José"

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A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems.

, , , , and . PIMRC, page 531-535. IEEE, (2004)

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Humberto Jorge José

Nadine José Gonzalez

José Navarrete

José Putharikal

José Schneider

 

Other publications of authors with the same name

High-speed NB-LDPC decoder for wireless applications., , and . ISPACS, page 215-220. IEEE, (2013)Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2., , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 494-504. Springer, (2004)Performance evaluation of fine time synchronizers for WLANs., , , and . EUSIPCO, page 1-4. IEEE, (2005)Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard., , , and . EUSIPCO, page 560-564. IEEE, (2007)DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems., , , , , , , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 988-991. Springer, (2003)Analysis and Contrast Between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation., , , and . SAPIR, volume 3126 of Lecture Notes in Computer Science, page 170-178. Springer, (2004)A 630 Mbps non-binary LDPC decoder for FPGA., , , , and . ISCAS, page 1989-1992. IEEE, (2015)Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN., , , , and . J. Signal Process. Syst., 52 (2): 181-191 (2008)64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm., , , and . ICECS, page 610-613. IEEE, (2008)Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN., , , , and . Journal of Circuits, Systems, and Computers, 18 (7): 1333-1337 (2009)