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%0 Journal Article
%1 journals/tcasII/HeYFHJWZSYL23
%A He, Yifan
%A Yue, Jinshan
%A Feng, Xiaoyu
%A Huang, Yuxuan
%A Jia, Hongyang
%A Wang, Jingyu
%A Zhang, Lu
%A Sun, Wenyu
%A Yang, Huazhong
%A Liu, Yongpan
%D 2023
%J IEEE Trans. Circuits Syst. II Express Briefs
%K dblp
%N 2
%P 416-420
%T An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.
%U http://dblp.uni-trier.de/db/journals/tcasII/tcasII70.html#HeYFHJWZSYL23
%V 70
@article{journals/tcasII/HeYFHJWZSYL23,
added-at = {2023-02-25T00:00:00.000+0100},
author = {He, Yifan and Yue, Jinshan and Feng, Xiaoyu and Huang, Yuxuan and Jia, Hongyang and Wang, Jingyu and Zhang, Lu and Sun, Wenyu and Yang, Huazhong and Liu, Yongpan},
biburl = {https://www.bibsonomy.org/bibtex/2f00d1d81b7f1ca78fda1a2293f93b3a4/dblp},
ee = {https://doi.org/10.1109/TCSII.2022.3209872},
interhash = {66ec8d4da22c4b805484ad98e478523e},
intrahash = {f00d1d81b7f1ca78fda1a2293f93b3a4},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
keywords = {dblp},
month = {February},
number = 2,
pages = {416-420},
timestamp = {2024-04-08T16:52:48.000+0200},
title = {An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.},
url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII70.html#HeYFHJWZSYL23},
volume = 70,
year = 2023
}
