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An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree.

, , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (2): 416-420 (February 2023)

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Register allocation for hybrid register architecture in nonvolatile processors., , , , , and . ISCAS, page 1050-1053. IEEE, (2014)A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing., , , , , , and . ISSCC, page 236-238. IEEE, (2021)Personalizing Statistical Models for Asthma Prognosis and Therapeutics., , , , and . AMIA, AMIA, (2014)An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (2): 416-420 (February 2023)An energy harvesting nonvolatile sensor node and its application to distributed moving object detection., , , , , , , and . IPSN, page 149-150. IEEE Computer Society / ACM, (2012)Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing., , , , , , and . IEEE J. Solid State Circuits, 57 (1): 198-211 (2022)A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing., , , , and . Hot Chips Symposium, page 1-29. IEEE, (2019)A Heterogeneous Microprocessor Based on All-Digital Compute-in-Memory for End-to-End AIoT Inference., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (8): 3099-3103 (August 2023)Data-Driven Security and Stability Rule in High Renewable Penetrated Power System Operation., , , , , , and . Proc. IEEE, 111 (7): 788-805 (July 2023)34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing., , , , , , , , , and 4 other author(s). ISSCC, page 578-580. IEEE, (2024)