%0 Journal Article %1 journals/jssc/VerbruggenCKWP10 %A Verbruggen, Bob %A Craninckx, Jan %A Kuijk, Maarten %A Wambacq, Piet %A der Plas, Geert Van %D 2010 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2080-2090 %T A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#VerbruggenCKWP10 %V 45

@article{journals/jssc/VerbruggenCKWP10, added-at = {2020-08-30T00:00:00.000+0200}, author = {Verbruggen, Bob and Craninckx, Jan and Kuijk, Maarten and Wambacq, Piet and der Plas, Geert Van}, biburl = {https://www.bibsonomy.org/bibtex/2990eea93e8b551931fa9abaf6d263298/dblp}, ee = {https://doi.org/10.1109/JSSC.2010.2061611}, interhash = {6c2648492df46aae18c5631c7e6992a9}, intrahash = {990eea93e8b551931fa9abaf6d263298}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2080-2090}, timestamp = {2020-08-31T11:40:24.000+0200}, title = {A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#VerbruggenCKWP10}, volume = 45, year = 2010 }