%0 Journal Article %1 journals/tvlsi/TsuiMPDDL96 %A Tsui, Chi-Ying %A Monteiro, José %A Pedram, Massoud %A Devadas, Srinivas %A Despain, Alvin M. %A Lin, Bill %D 1996 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 4 %P 495 %T Correction to "Power Estimation Methods for Sequential Logic Circuits" Correspondence. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi4.html#TsuiMPDDL96 %V 4

@article{journals/tvlsi/TsuiMPDDL96, added-at = {2022-08-01T00:00:00.000+0200}, author = {Tsui, Chi-Ying and Monteiro, José and Pedram, Massoud and Devadas, Srinivas and Despain, Alvin M. and Lin, Bill}, biburl = {https://www.bibsonomy.org/bibtex/2fee2d5e7e244cf5c8447f529761516a5/dblp}, ee = {https://doi.org/10.1109/TVLSI.1996.544414}, interhash = {77424699339403d039da19f561cdbba4}, intrahash = {fee2d5e7e244cf5c8447f529761516a5}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 4, pages = 495, timestamp = {2024-04-08T14:32:54.000+0200}, title = {Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi4.html#TsuiMPDDL96}, volume = 4, year = 1996 }