%0 Journal Article %1 journals/tcasII/LinTGQZQW23 %A Lin, Yudeng %A Tang, Jianshi %A Gao, Bin %A Qin, Qi %A Zhang, Qingtian %A Qian, He %A Wu, Huaqiang %D 2023 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 4 %P 1366-1370 %T A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII70.html#LinTGQZQW23 %V 70

@article{journals/tcasII/LinTGQZQW23, added-at = {2023-07-27T00:00:00.000+0200}, author = {Lin, Yudeng and Tang, Jianshi and Gao, Bin and Qin, Qi and Zhang, Qingtian and Qian, He and Wu, Huaqiang}, biburl = {https://www.bibsonomy.org/bibtex/2aa12201c0c958f40947d3ce1d1909031/dblp}, ee = {https://doi.org/10.1109/TCSII.2022.3224470}, interhash = {77fda92527f27eb89142e8f1023c7085}, intrahash = {aa12201c0c958f40947d3ce1d1909031}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, month = {April}, number = 4, pages = {1366-1370}, timestamp = {2024-04-08T16:53:13.000+0200}, title = {A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII70.html#LinTGQZQW23}, volume = 70, year = 2023 }