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A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.

Y. Lin, J. Tang, B. Gao, Q. Qin, Q. Zhang, H. Qian, and H. Wu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (4): 1366-1370 (April 2023)

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Jianshi Liu

Tang Tang

Fei Tang

Jian Tang

Junhua Tang

Other publications of authors with the same name

A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.B. Lin, Y. Pang, B. Gao, J. Tang, D. Wu, T. Chang, W. Lin, X. Sun, S. Yu, M. Chang and 2 other author(s). IEEE J. Solid State Circuits, 56 (5): 1641-1650 (2021)Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips.Y. Liu, B. Gao, J. Tang, H. Wu, and H. Qian. Sci. China Inf. Sci., (October 2023)Generic Cryo-CMOS Device Modeling and EDACompatible Platform for Reliable Cryogenic IC Design.Z. Wang, Z. Tang, Y. Yuan, A. Guo, X. Luo, R. Chen, C. Cao, L. Liu, Z. Zhi, W. Wu and 10 other author(s). CoRR, (2022)Adaptive optimal output regulation for wheel-legged robot Ollie: A data-driven approach.J. Zhang, Z. Li, S. Wang, Y. Dai, R. Zhang, J. Lai, D. Zhang, K. Chen, J. Hu, W. Gao and 2 other author(s). Frontiers Neurorobotics, (September 2022)BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment.Y. Lin, J. Tang, B. Gao, Q. Zhang, H. Qian, and H. Wu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (6): 1846-1850 (June 2023)An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.H. Gong, H. He, L. Pan, B. Gao, J. Tang, S. Pan, J. Li, P. Yao, D. Wu, H. Qian and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 5339-5351 (December 2023)An RRAM retention prediction framework using a convolutional neural network based on relaxation behavior.Y. Zhang, Q. Zhang, Q. Qin, W. Zhang, Y. Xi, Z. Jiang, J. Tang, B. Gao, H. Qian, and H. Wu. Neuromorph. Comput. Eng., 3 (1): 14011 (March 2023)HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU.Y. Jiang, B. Gao, J. Tang, D. Wu, H. He, H. Qian, and H. Wu. ICTA, page 35-36. IEEE, (2021)Thermal Induced Retention Degradation of RRAM-based Neuromorphic Computing Chips.A. Ma, B. Gao, X. Mou, P. Yao, Y. Du, J. Tang, H. Qian, and H. Wu. IRPS, page 1-6. IEEE, (2023)Impact of Bottom Electrode Roughness on the Analog Switching Characteristics in Nanoscale RRAM Array.W. Zhang, J. Tang, B. Gao, W. Sun, W. Liu, K. Wang, W. Wu, H. Qian, and H. Wu. DRC, page 1-2. IEEE, (2021)

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Disambiguation of "Tang, Jianshi"

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A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.

Please choose a person to relate this publication to

Jianshi Liu

Tang Tang

Fei Tang

Jian Tang

Junhua Tang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tang, Jianshi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.

Please choose a person to relate this publication to

Jianshi Liu

Tang Tang

Fei Tang

Jian Tang

Junhua Tang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator.