%0 Conference Paper %1 conf/icassp/RehmanSCC14 %A ur Rehman, Saeed %A Sani, Awais %A Chavet, Cyrille %A Coussy, Philippe %B ICASSP %D 2014 %I IEEE %K dblp %P 5036-5040 %T Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. %U http://dblp.uni-trier.de/db/conf/icassp/icassp2014.html#RehmanSCC14

@inproceedings{conf/icassp/RehmanSCC14, added-at = {2017-05-19T00:00:00.000+0200}, author = {ur Rehman, Saeed and Sani, Awais and Chavet, Cyrille and Coussy, Philippe}, biburl = {https://www.bibsonomy.org/bibtex/2734fb3392feb01bdb8061d5c2642ae06/dblp}, booktitle = {ICASSP}, crossref = {conf/icassp/2014}, ee = {https://doi.org/10.1109/ICASSP.2014.6854561}, interhash = {801e3cf44b92fbfc09096767a295dad5}, intrahash = {734fb3392feb01bdb8061d5c2642ae06}, keywords = {dblp}, pages = {5036-5040}, publisher = {IEEE}, timestamp = {2019-10-17T17:19:15.000+0200}, title = {Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.}, url = {http://dblp.uni-trier.de/db/conf/icassp/icassp2014.html#RehmanSCC14}, year = 2014 }