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Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.

S. ur Rehman, A. Sani, C. Chavet, and P. Coussy. ICASSP, page 5036-5040. IEEE, (2014)

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Philippe Destouches

Philippe Staib

Philippe Bopp

Philippe Moisan

Philippe Kersting

Other publications of authors with the same name

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.O. Sanchez, M. Jézéquel, S. ur Rehman, A. Sani, C. Chavet, P. Coussy, and C. Jégo. SiPS, page 288-293. IEEE, (2012)Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.S. ur Rehman, A. Sani, C. Chavet, and P. Coussy. ICASSP, page 5036-5040. IEEE, (2014)Bitwidth-aware high-level synthesis for designing low-power DSP applications.G. Lhairech-Lebreton, P. Coussy, D. Heller, and E. Martin. ICECS, page 531-534. IEEE, (2010)A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator.M. Hammouda, P. Coussy, and L. Lagadec. ACM Great Lakes Symposium on VLSI, page 273-278. ACM, (2014)An Introduction to High-Level Synthesis.P. Coussy, D. Gajski, M. Meredith, and A. Takach. IEEE Des. Test Comput., 26 (4): 8-17 (2009)Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder.P. Coussy, A. Baganne, and E. Martin. ICECS, page 733-736. IEEE, (2002)Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system.F. Thabet, P. Coussy, D. Heller, and E. Martin. EUSIPCO, page 1625-1629. IEEE, (2007)A memory mapping approach for network and controller optimization in parallel interleaver architectures.A. Briki, C. Chavet, and P. Coussy. ACM Great Lakes Symposium on VLSI, page 321-322. ACM, (2013)Solving Memory Access Conflicts in LTE-4G Standard.C. Chavet, F. Lozachmeur, T. Barguil, A. Hussein, and P. Coussy. ICASSP, page 1518-1522. IEEE, (2019)A design methodology for IP integration.P. Coussy, A. Baganne, and E. Martin. ISCAS (4), page 711-714. IEEE, (2002)

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Disambiguation of "Coussy, Philippe"

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Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.

Please choose a person to relate this publication to

Philippe Destouches

Philippe Staib

Philippe Bopp

Philippe Moisan

Philippe Kersting

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Coussy, Philippe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.

Please choose a person to relate this publication to

Philippe Destouches

Philippe Staib

Philippe Bopp

Philippe Moisan

Philippe Kersting

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.