%0 Journal Article %1 journals/jcsc/AgrawalJ16 %A Agrawal, Rekha %A Jain, Shailendra %D 2016 %J Journal of Circuits, Systems, and Computers %K dblp %N 7 %P 1650081:1-1650081:18 %T Suitability of Reduced Part Count Multilevel Inverter Topologies for Grid Interfacing. %U http://dblp.uni-trier.de/db/journals/jcsc/jcsc25.html#AgrawalJ16 %V 25

@article{journals/jcsc/AgrawalJ16, added-at = {2019-12-18T00:00:00.000+0100}, author = {Agrawal, Rekha and Jain, Shailendra}, biburl = {https://www.bibsonomy.org/bibtex/2b01df4b65f863b8636d673576777270e/dblp}, ee = {https://doi.org/10.1142/S021812661650081X}, interhash = {94a2dbc0371790764a0d04842b3b751f}, intrahash = {b01df4b65f863b8636d673576777270e}, journal = {Journal of Circuits, Systems, and Computers}, keywords = {dblp}, number = 7, pages = {1650081:1-1650081:18}, timestamp = {2019-12-19T11:44:05.000+0100}, title = {Suitability of Reduced Part Count Multilevel Inverter Topologies for Grid Interfacing.}, url = {http://dblp.uni-trier.de/db/journals/jcsc/jcsc25.html#AgrawalJ16}, volume = 25, year = 2016 }