%0 Conference Paper %1 conf/isscc/KimPKKPJ13 %A Kim, Wooseok %A Park, Jaejin %A Kim, Jihyun F. %A Kim, Taeik %A Park, Hojin %A Jeong, Deog-Kyoon %B ISSCC %D 2013 %I IEEE %K dblp %P 250-251 %T A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2013.html#KimPKKPJ13 %@ 978-1-4673-4515-6

@inproceedings{conf/isscc/KimPKKPJ13, added-at = {2017-05-17T00:00:00.000+0200}, author = {Kim, Wooseok and Park, Jaejin and Kim, Jihyun F. and Kim, Taeik and Park, Hojin and Jeong, Deog-Kyoon}, biburl = {https://www.bibsonomy.org/bibtex/2f14e003fd4f9f3f5ccab00b09ab5dc29/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2013}, ee = {https://doi.org/10.1109/ISSCC.2013.6487721}, interhash = {9837a42c341182cffe31fb26dcfd8bf3}, intrahash = {f14e003fd4f9f3f5ccab00b09ab5dc29}, isbn = {978-1-4673-4515-6}, keywords = {dblp}, pages = {250-251}, publisher = {IEEE}, timestamp = {2017-05-18T22:15:17.000+0200}, title = {A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2013.html#KimPKKPJ13}, year = 2013 }