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Disambiguation of "Park, Jaejin"

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A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.

, , , , , and . ISSCC, page 250-251. IEEE, (2013)

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Rosemary Park

Sungjune Park

Eunhong Park

Younggyu Park

Hyeyoung Park

 

Other publications of authors with the same name

A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem., , , , and . IEEE J. Solid State Circuits, 30 (8): 940-943 (August 1995)A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR., , , and . CICC, page 281-284. IEEE, (2007)A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter., , , , and . ISCAS, page 319-322. IEEE, (1994)A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications., , , , , , , , and . ISSCC, page 240-242. IEEE, (2012)A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range., , , , , and . ISSCC, page 250-251. IEEE, (2013)A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs., , , and . ISCAS (2), page 1162-1165. IEEE, (2005)A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 655-659 (2017)A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter., , , , , , , , and . ISSCC, page 254-255. IEEE, (2013)Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator., , , and . IEEE J. Solid State Circuits, 49 (3): 657-672 (2014)CFGP: a web-based, comparative fungal genomics platform., , , , , , , , , and 6 other author(s). Nucleic Acids Res., 36 (Database-Issue): 562-571 (2008)