%0 Journal Article %1 journals/tcad/KunzSM97 %A Kunz, Wolfgang %A Stoffel, Dominik %A Menon, Prem R. %D 1997 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 3 %P 266-281 %T Logic optimization and equivalence checking by implication analysis. %U http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#KunzSM97 %V 16

@article{journals/tcad/KunzSM97, added-at = {2020-11-11T00:00:00.000+0100}, author = {Kunz, Wolfgang and Stoffel, Dominik and Menon, Prem R.}, biburl = {https://www.bibsonomy.org/bibtex/2ff88740cdc4040e35c16bf94f54892ff/dblp}, ee = {https://doi.org/10.1109/43.594832}, interhash = {a6058a98633d5b6eb8e22a5f8f6a57d1}, intrahash = {ff88740cdc4040e35c16bf94f54892ff}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 3, pages = {266-281}, timestamp = {2020-11-12T11:35:16.000+0100}, title = {Logic optimization and equivalence checking by implication analysis.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#KunzSM97}, volume = 16, year = 1997 }