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Logic optimization and equivalence checking by implication analysis.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (3): 266-281 (1997)

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Divergence and scheduling in functional level concurrent fault simulation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (5): 734-736 (1993)Multi-level logic optimization by implication analysis., and . ICCAD, page 6-13. IEEE Computer Society / ACM, (1994)Structural Simplification and Decomposition of Asynchronous Sequential Circuits, , and . SWAT, page 7-19. IEEE Computer Society, (1968)System-level design verification in the AT&T Computer Division: tools., , , and . ICCD, page 548-554. IEEE, (1989)Redundancy removal and simplification of combinational circuits., and . VTS, page 268-273. IEEE Computer Society, (1992)A Practical Approach to Fault Simulation and Test Generation for Bridging Faults., and . IEEE Trans. Computers, 34 (7): 658-663 (1985)Systems of Asynchronously Operating Modules., and . IEEE Trans. Computers, 20 (1): 100-104 (1971)Identification of undetectable faults in combinational circuits., and . ICCD, page 290-293. IEEE, (1989)Fault simulation on reconfigurable hardware., and . FCCM, page 182-191. IEEE Computer Society, (1997)A logic simulation machine., , and . ISCA, page 148-157. IEEE Computer Society, (1982)