%0 Conference Paper %1 song2016unified %A Song, S. C. %A Xu, J. %A Yang, D. %A Rim, K. %A Feng, P. %A Bao, J. %A Zhu, J. %A Wang, J. %A Nallapati, G. %A Badaroglu, M. %A Narayanasetti, P. %A Bucki, B. %A Fischer, J. %A Yeap, G. %B IEEE Symposium on VLSI Circuits (VLSI-Circuits) %D 2016 %K techopt %P 1-2 %R 10.1109/VLSIC.2016.7573515 %T Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at amp;lt;= 7nm nodes %X We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.

@inproceedings{song2016unified, abstract = {We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.}, added-at = {2018-08-20T14:26:40.000+0200}, author = {Song, S. C. and Xu, J. and Yang, D. and Rim, K. and Feng, P. and Bao, J. and Zhu, J. and Wang, J. and Nallapati, G. and Badaroglu, M. and Narayanasetti, P. and Bucki, B. and Fischer, J. and Yeap, G.}, biburl = {https://www.bibsonomy.org/bibtex/2e93ae95d7dee38ee7bcfee7f5dcc8535/ahari}, booktitle = {IEEE Symposium on VLSI Circuits (VLSI-Circuits)}, description = {Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes - IEEE Conference Publication}, doi = {10.1109/VLSIC.2016.7573515}, interhash = {b1608ecd157ad8573b68e43c5b503a16}, intrahash = {e93ae95d7dee38ee7bcfee7f5dcc8535}, keywords = {techopt}, month = {June}, pages = {1-2}, timestamp = {2018-08-22T11:12:16.000+0200}, title = {Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at amp;lt;= 7nm nodes}, year = 2016 }