%0 Journal Article %1 journals/jssc/HaighWMBSC05 %A Haigh, Jonathan R. %A Wilkerson, Michael W. %A Miller, Jay B. %A Beatty, Timothy S. %A Strazdus, Stephen J. %A Clark, Lawrence T. %D 2005 %J IEEE J. Solid State Circuits %K dblp %N 5 %P 1190-1199 %T A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. %U http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#HaighWMBSC05 %V 40

@article{journals/jssc/HaighWMBSC05, added-at = {2022-03-02T00:00:00.000+0100}, author = {Haigh, Jonathan R. and Wilkerson, Michael W. and Miller, Jay B. and Beatty, Timothy S. and Strazdus, Stephen J. and Clark, Lawrence T.}, biburl = {https://www.bibsonomy.org/bibtex/200562d3c30fb81c6c358ec6c6284b362/dblp}, ee = {https://doi.org/10.1109/JSSC.2005.845971}, interhash = {bcbdbf725abefd31eb3a4f0af32bdc98}, intrahash = {00562d3c30fb81c6c358ec6c6284b362}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 5, pages = {1190-1199}, timestamp = {2024-04-08T10:42:05.000+0200}, title = {A low-power 2.5-GHz 90-nm level 1 cache and memory management unit.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#HaighWMBSC05}, volume = 40, year = 2005 }