Article,
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.
C. Lee, H. Chi, J. Heo, J. Park, J. Jang, D. Lee, J. Jung, D. Lee, D. Kim, K. Kim, S. Kim, D. Park, Y. Lim, G. Park, S. Lee, S. Hong, D. Kwon, I. Hwang, B. Na, K. Kim, S. Choi, H. Choi, Hangi-Jung, W. Bae, J. Ihm, S. Bae, N. Kim, and J. Lee.IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)
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- IEEE J. Solid State Circuits
- number
- 1
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- 212-224
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- 56
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- https://doi.org/10.1109/JSSC.2020.3017775
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- http://dblp.uni-trier.de/db/journals/jssc/jssc56.html#LeeCHPJLJLKKKPL21
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%1 journals/jssc/LeeCHPJLJLKKKPL21
%A Lee, Chang-Kyo
%A Chi, Hyung-Joon
%A Heo, Jin-Seok
%A Park, Junghwan
%A Jang, Jin-Hun
%A Lee, Dongkeon
%A Jung, Jaehoon
%A Lee, Dong-Hun
%A Kim, Dae-Hyun
%A Kim, Kihan
%A Kim, Sang-Yun
%A Park, Dukha
%A Lim, Youngil
%A Park, Geuntae
%A Lee, Seungjun
%A Hong, Seungki
%A Kwon, Dae-Hyun
%A Hwang, Isak
%A Na, Byongwook
%A Kim, Kyungryun
%A Choi, Seouk-Kyu
%A Choi, Hye-In
%A Hangi-Jung,
%A Bae, Wonil
%A Ihm, Jeong-Don
%A Bae, Seung-Jun
%A Kim, Nam Sung
%A Lee, Jung-Bae
%D 2021
%J IEEE J. Solid State Circuits
%K dblp
%N 1
%P 212-224
%T An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc56.html#LeeCHPJLJLKKKPL21
%V 56
@article{journals/jssc/LeeCHPJLJLKKKPL21,
added-at = {2024-03-05T00:00:00.000+0100},
author = {Lee, Chang-Kyo and Chi, Hyung-Joon and Heo, Jin-Seok and Park, Junghwan and Jang, Jin-Hun and Lee, Dongkeon and Jung, Jaehoon and Lee, Dong-Hun and Kim, Dae-Hyun and Kim, Kihan and Kim, Sang-Yun and Park, Dukha and Lim, Youngil and Park, Geuntae and Lee, Seungjun and Hong, Seungki and Kwon, Dae-Hyun and Hwang, Isak and Na, Byongwook and Kim, Kyungryun and Choi, Seouk-Kyu and Choi, Hye-In and Hangi-Jung and Bae, Wonil and Ihm, Jeong-Don and Bae, Seung-Jun and Kim, Nam Sung and Lee, Jung-Bae},
biburl = {https://www.bibsonomy.org/bibtex/21013840dd77e29086533ef2bd95e23a3/dblp},
ee = {https://doi.org/10.1109/JSSC.2020.3017775},
interhash = {c7861a615b4ae3e968785949b108af57},
intrahash = {1013840dd77e29086533ef2bd95e23a3},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 1,
pages = {212-224},
timestamp = {2024-04-08T10:44:42.000+0200},
title = {An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc56.html#LeeCHPJLJLKKKPL21},
volume = 56,
year = 2021
}