%0 Conference Paper %1 conf/socc/HongCZJWL14 %A Hong, Chi-Hao %A Chiu, Yi-Wei %A Zhao, Jun-Kai %A Jou, Shyh-Jye %A Wang, Wen-Tai %A Lee, Reed %B SoCC %D 2014 %E Shi, Kaijian %E Büchner, Thomas %E Zhao, Danella %E Sridhar, Ramalingam %I IEEE %K dblp %P 160-164 %T A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. %U http://dblp.uni-trier.de/db/conf/socc/socc2014.html#HongCZJWL14 %@ 978-1-4799-3378-5

@inproceedings{conf/socc/HongCZJWL14, added-at = {2014-11-10T00:00:00.000+0100}, author = {Hong, Chi-Hao and Chiu, Yi-Wei and Zhao, Jun-Kai and Jou, Shyh-Jye and Wang, Wen-Tai and Lee, Reed}, biburl = {https://www.bibsonomy.org/bibtex/20914a12597f978080ce6da89224603b4/dblp}, booktitle = {SoCC}, crossref = {conf/socc/2014}, editor = {Shi, Kaijian and Büchner, Thomas and Zhao, Danella and Sridhar, Ramalingam}, ee = {http://dx.doi.org/10.1109/SOCC.2014.6948919}, interhash = {cc0392920707f329c64eca54ca4449a4}, intrahash = {0914a12597f978080ce6da89224603b4}, isbn = {978-1-4799-3378-5}, keywords = {dblp}, pages = {160-164}, publisher = {IEEE}, timestamp = {2016-02-23T11:55:58.000+0100}, title = {A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.}, url = {http://dblp.uni-trier.de/db/conf/socc/socc2014.html#HongCZJWL14}, year = 2014 }