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A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.

C. Hong, Y. Chiu, J. Zhao, S. Jou, W. Wang, and R. Lee. SoCC, page 160-164. IEEE, (2014)

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Yi Wei

Wei-Hua Chiu

Wei-Chen Chiu

Wei-Hua Chiu

Other publications of authors with the same name

A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.C. Hong, Y. Chiu, J. Zhao, S. Jou, W. Wang, and R. Lee. SoCC, page 160-164. IEEE, (2014)40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.Y. Chiu, Y. Hu, M. Tu, J. Zhao, Y. Chu, S. Jou, and C. Chuang. IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (9): 2578-2585 (2014)On the fuzzified quorum-based wakeup scheduling in heterogeneous wireless sensor network.C. Own, and C. Wei. ISCE, page 143-144. IEEE, (2013)AI Powered Multi-model Content Creation For Virtual Gallery Using Learning Machine.Y. Chen, Y. Chiu, Y. Liu, C. Huang, and Y. Shen. UEMCON, page 704-709. IEEE, (2023)8T single-ended sub-threshold SRAM with cross-point data-aware write operation.Y. Chiu, J. Lin, M. Tu, S. Jou, and C. Chuang. ISLPED, page 169-174. IEEE/ACM, (2011)A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.Y. Chiu, Y. Hu, M. Tu, J. Zhao, S. Jou, and C. Chuang. ISLPED, page 51-56. IEEE, (2013)A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.L. Wang, Y. Chiu, C. Hu, M. Tu, S. Jou, and C. Lee. ISCAS, page 3426-3429. IEEE, (2008)Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM.S. Wang, G. Lin, Y. Lin, M. Tsai, Y. Chiu, S. Jou, C. Chuang, N. Lien, W. Shih, K. Lee and 1 other author(s). APCCAS, page 116-119. IEEE, (2012)A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.C. Hong, Y. Chiu, J. Zhao, S. Jou, W. Wang, and R. Lee. ISCAS, page 2549-2552. IEEE, (2015)

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Disambiguation of "Chiu, Yi-Wei"

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A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.

Please choose a person to relate this publication to

Yi Wei

Yi Wei

Wei-Hua Chiu

Wei-Chen Chiu

Wei-Hua Chiu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chiu, Yi-Wei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.

Please choose a person to relate this publication to

Yi Wei

Yi Wei

Wei-Hua Chiu

Wei-Chen Chiu

Wei-Hua Chiu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.