%0 Journal Article %1 journals/aisy/CaiYUTLFZLKHA22 %A Cai, Fuxi %A Yen, She-Hwa %A Uppala, Apurva %A Thomas, Luke %A Liu, Tianchi %A Fu, Peter %A Zhang, Xiaofeng %A Low, Ambrose %A Kamalanathan, Deepak %A Hsu, Joe %A Ayyagari-Sangamalli, Buvna %D 2022 %J Adv. Intell. Syst. %K dblp %N 8 %T A Fully Integrated System-on-Chip Design with Scalable Resistive Random-Access Memory Tile Design for Analog in-Memory Computing. %U http://dblp.uni-trier.de/db/journals/aisy/aisy4.html#CaiYUTLFZLKHA22 %V 4

@article{journals/aisy/CaiYUTLFZLKHA22, added-at = {2022-10-07T00:00:00.000+0200}, author = {Cai, Fuxi and Yen, She-Hwa and Uppala, Apurva and Thomas, Luke and Liu, Tianchi and Fu, Peter and Zhang, Xiaofeng and Low, Ambrose and Kamalanathan, Deepak and Hsu, Joe and Ayyagari-Sangamalli, Buvna}, biburl = {https://www.bibsonomy.org/bibtex/281276e9d19632982593a1d19f6caa009/dblp}, ee = {https://doi.org/10.1002/aisy.202200014}, interhash = {d12f1b4e1c9d01930e4551f5e104d5bb}, intrahash = {81276e9d19632982593a1d19f6caa009}, journal = {Adv. Intell. Syst.}, keywords = {dblp}, number = 8, timestamp = {2024-04-08T21:10:54.000+0200}, title = {A Fully Integrated System-on-Chip Design with Scalable Resistive Random-Access Memory Tile Design for Analog in-Memory Computing.}, url = {http://dblp.uni-trier.de/db/journals/aisy/aisy4.html#CaiYUTLFZLKHA22}, volume = 4, year = 2022 }