%0 Journal Article %1 journals/tcad/PullelaMP97 %A Pullela, Satyamurthy %A Menezes, Noel %A Pileggi, Lawrence T. %D 1997 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 2 %P 210-215 %T Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. %U http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#PullelaMP97 %V 16

@article{journals/tcad/PullelaMP97, added-at = {2020-09-24T00:00:00.000+0200}, author = {Pullela, Satyamurthy and Menezes, Noel and Pileggi, Lawrence T.}, biburl = {https://www.bibsonomy.org/bibtex/2158ffa1fb1e0085e4a9e0489f1d013f8/dblp}, ee = {https://doi.org/10.1109/43.573836}, interhash = {d90105dc8f60cc6d4491f6e429b02686}, intrahash = {158ffa1fb1e0085e4a9e0489f1d013f8}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 2, pages = {210-215}, timestamp = {2020-09-25T11:48:50.000+0200}, title = {Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#PullelaMP97}, volume = 16, year = 1997 }