%0 Journal Article %1 journals/corr/SahaBMS13 %A Saha, Dipankar %A Basak, Subhramita %A Mukherjee, Sagar %A Sarkar, Chandan Kumar %D 2013 %J CoRR %K dblp %T A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. %U http://dblp.uni-trier.de/db/journals/corr/corr1309.html#SahaBMS13 %V abs/1309.7163

@article{journals/corr/SahaBMS13, added-at = {2018-08-13T00:00:00.000+0200}, author = {Saha, Dipankar and Basak, Subhramita and Mukherjee, Sagar and Sarkar, Chandan Kumar}, biburl = {https://www.bibsonomy.org/bibtex/2570f80e1f9a4c9b540b6228045094576/dblp}, ee = {http://arxiv.org/abs/1309.7163}, interhash = {ed1dd46aa603f8fc1bb465d33c216fed}, intrahash = {570f80e1f9a4c9b540b6228045094576}, journal = {CoRR}, keywords = {dblp}, timestamp = {2018-08-14T12:38:45.000+0200}, title = {A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme.}, url = {http://dblp.uni-trier.de/db/journals/corr/corr1309.html#SahaBMS13}, volume = {abs/1309.7163}, year = 2013 }