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Disambiguation of "Saha, Dipankar"

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A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme.

, , , and . CoRR, (2013)

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Dipankar Mandal

Janapriya Saha

Susanne Saha

Sankalita Saha

Joyanta Saha

 

Other publications of authors with the same name

Organic User Interfaces: Framework, Interaction Model and Design Guidelines, and . International Journal of Ad hoc, Sensor & Ubiquitous Computing (IJASUC), 4 (4): 20 (August 2013)Performance Evaluation on Extended Routing Protocol of AODV in Manet, and . International Journal of Ad hoc, Sensor & Ubiquitous Computing (IJASUC), 4 (4): 11 (August 2013)A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications., , , , and . ISED, page 28-32. IEEE, (2012)Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme., , , , and . ISED, page 130-134. IEEE, (2012)New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact., , and . VLSID, page 139-142. IEEE Computer Society, (2018)Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit., , , , and . CoRR, (2013)Loss Reduction in a Grid-Connected Photovoltaic System Operated with P-&-O Algorithm based MPPT Control by introducing Diamond MOSFET., , , , and . ISDCS, page 1-6. IEEE, (2021)SQL Injection Attack Mechanisms and Prevention Techniques., , , and . ADCONS, volume 7135 of Lecture Notes in Computer Science, page 524-533. Springer, (2011)Atomistic Analysis of Receptor Structure in Quantum Biomimetic Olfactory Sensor., , , and . IEEE SENSORS, page 1-4. IEEE, (2018)Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2., , , , and . VDAT, page 1-6. IEEE, (2021)