%0 Conference Paper %1 conf/ieeehpcs/HuangHTC16 %A Huang, Shi-Yu %A Huang, Tzu-Heng %A Tsai, Kun-Han %A Cheng, Wu-Tung %B HPCS %D 2016 %I IEEE %K dblp %P 125-129 %T A wide-range clock signal generation scheme for speed grading of a logic core. %U http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#HuangHTC16 %@ 978-1-5090-2088-1

@inproceedings{conf/ieeehpcs/HuangHTC16, added-at = {2016-09-19T00:00:00.000+0200}, author = {Huang, Shi-Yu and Huang, Tzu-Heng and Tsai, Kun-Han and Cheng, Wu-Tung}, biburl = {https://www.bibsonomy.org/bibtex/2d0fbda80148a2dd3dd029af1c0b3eb42/dblp}, booktitle = {HPCS}, crossref = {conf/ieeehpcs/2016}, ee = {http://dx.doi.org/10.1109/HPCSim.2016.7568325}, interhash = {fb308e0c5988068f37f95d819a242ed5}, intrahash = {d0fbda80148a2dd3dd029af1c0b3eb42}, isbn = {978-1-5090-2088-1}, keywords = {dblp}, pages = {125-129}, publisher = {IEEE}, timestamp = {2016-09-20T11:36:09.000+0200}, title = {A wide-range clock signal generation scheme for speed grading of a logic core.}, url = {http://dblp.uni-trier.de/db/conf/ieeehpcs/ieeehpcs2016.html#HuangHTC16}, year = 2016 }