%0 Conference Paper %1 conf/iscas/HarounW94 %A Haroun, Baher %A Wu, Chao Hua %B ISCAS %D 1994 %I IEEE %K dblp %P 9-12 %T A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. %U http://dblp.uni-trier.de/db/conf/iscas/iscas1994-2.html#HarounW94 %@ 0-7803-1916-8

@inproceedings{conf/iscas/HarounW94, added-at = {2016-05-23T00:00:00.000+0200}, author = {Haroun, Baher and Wu, Chao Hua}, biburl = {https://www.bibsonomy.org/bibtex/2d53caf27bfb44b0401eb9569ad9c70d9/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/1994}, ee = {http://dx.doi.org/10.1109/ISCAS.1994.408892}, interhash = {fdcf3de58cdbf65e33f654e92a1e9413}, intrahash = {d53caf27bfb44b0401eb9569ad9c70d9}, isbn = {0-7803-1916-8}, keywords = {dblp}, pages = {9-12}, publisher = {IEEE}, timestamp = {2016-05-24T11:51:44.000+0200}, title = {A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas1994-2.html#HarounW94}, year = 1994 }