%0 Journal Article %1 journals/jssc/McAndrewHC09 %A McAndrew, Colin C. %A Huszka, Zoltan %A Coram, Geoffrey J. %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 9 %P 2267-2275 %T Bipolar Transistor Excess Phase Modeling in Verilog-A. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#McAndrewHC09 %V 44

@article{journals/jssc/McAndrewHC09, added-at = {2020-08-30T00:00:00.000+0200}, author = {McAndrew, Colin C. and Huszka, Zoltan and Coram, Geoffrey J.}, biburl = {https://www.bibsonomy.org/bibtex/2314a94f452db23d879401f94ba82acef/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2022667}, interhash = {b517908ac10673068973a304ea4f872e}, intrahash = {314a94f452db23d879401f94ba82acef}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 9, pages = {2267-2275}, timestamp = {2020-08-31T11:42:23.000+0200}, title = {Bipolar Transistor Excess Phase Modeling in Verilog-A.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#McAndrewHC09}, volume = 44, year = 2009 }