%0 Conference Paper %1 conf/aspdac/ZhangSTH99 %A Zhang, Kai %A Shinogi, Tsuyoshi %A Takase, Haruhiko %A Hayashi, Terumine %B ASP-DAC %D 1999 %I IEEE Computer Society %K dblp %P 291-294 %T A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac1999.html#ZhangSTH99 %@ 0-7803-5012-X

@inproceedings{conf/aspdac/ZhangSTH99, added-at = {2023-03-23T00:00:00.000+0100}, author = {Zhang, Kai and Shinogi, Tsuyoshi and Takase, Haruhiko and Hayashi, Terumine}, biburl = {https://www.bibsonomy.org/bibtex/2e73584b52ed8f38a6da887d2f2068824/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/1999}, ee = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.760016}, interhash = {268318e8246f3d5e2c63365e587d8898}, intrahash = {e73584b52ed8f38a6da887d2f2068824}, isbn = {0-7803-5012-X}, keywords = {dblp}, pages = {291-294}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T20:42:58.000+0200}, title = {A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac1999.html#ZhangSTH99}, year = 1999 }