%0 Conference Paper %1 conf/iscas/RuanLCTL01 %A Ruan, Shanq-Jang %A Lin, Jen-Chiun %A Chen, Po-Hung %A Tsai, Kun-Lin %A Lai, Feipei %B ISCAS (5) %D 2001 %I IEEE %K dblp %P 523-526 %T Synthesis of partition-codec architecture for low power and small area circuit design. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2001-5.html#RuanLCTL01 %@ 0-7803-6685-9

@inproceedings{conf/iscas/RuanLCTL01, added-at = {2021-04-09T00:00:00.000+0200}, author = {Ruan, Shanq-Jang and Lin, Jen-Chiun and Chen, Po-Hung and Tsai, Kun-Lin and Lai, Feipei}, biburl = {https://www.bibsonomy.org/bibtex/2691bb10625033b9d19e4e90e70133912/dblp}, booktitle = {ISCAS (5)}, crossref = {conf/iscas/2001}, ee = {https://doi.org/10.1109/ISCAS.2001.922100}, interhash = {e38c7c3368c25902a7025d6ec710be9a}, intrahash = {691bb10625033b9d19e4e90e70133912}, isbn = {0-7803-6685-9}, keywords = {dblp}, pages = {523-526}, publisher = {IEEE}, timestamp = {2024-04-10T17:44:33.000+0200}, title = {Synthesis of partition-codec architecture for low power and small area circuit design.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2001-5.html#RuanLCTL01}, year = 2001 }