%0 Journal Article %1 journals/tcad/BanerjeeSB09 %A Banerjee, Pritha %A Sur-Kolay, Susmita %A Bishnu, Arijit %D 2009 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 5 %P 651-661 %T Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. %U http://dblp.uni-trier.de/db/journals/tcad/tcad28.html#BanerjeeSB09 %V 28

@article{journals/tcad/BanerjeeSB09, added-at = {2020-09-24T00:00:00.000+0200}, author = {Banerjee, Pritha and Sur-Kolay, Susmita and Bishnu, Arijit}, biburl = {https://www.bibsonomy.org/bibtex/28a7a7d347ba460c2087295095d3ea92c/dblp}, ee = {https://doi.org/10.1109/TCAD.2009.2015738}, interhash = {d69da2b90517fe6ca43285026a7be3da}, intrahash = {8a7a7d347ba460c2087295095d3ea92c}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 5, pages = {651-661}, timestamp = {2020-09-25T11:50:13.000+0200}, title = {Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad28.html#BanerjeeSB09}, volume = 28, year = 2009 }