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Disambiguation of "Banerjee, Pritha"

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Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (5): 651-661 (2009)

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Pritha Mahata

Abhishek Banerjee

Prabuddha Banerjee

Mita Banerjee

Nandakishore Banerjee

 

Other publications of authors with the same name

Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges., and . Microelectron. J., (2022)Stitch-avoiding Global Routing for Multiple E-Beam Lithography., , , and . VLSID, page 138-143. IEEE, (2022)Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography., , and . ICCD, page 411-414. IEEE Computer Society, (2017)Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification., , and . ISVLSI, page 212-217. IEEE, (2019)Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (5): 651-661 (2009)FPGA placement using space-filling curves: Theory meets practice., , , , , and . ACM Trans. Embed. Comput. Syst., 9 (2): 12:1-12:23 (2009)Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal-oxide-semiconductor field-effect transistor., , and . IET Circuits Devices Syst., 12 (5): 557-562 (2018)Floorplanning for Partial Reconfiguration in FPGAs., , and . VLSI Design, page 125-130. IEEE Computer Society, (2009)Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction., , , and . Integr., (2023)An efficient and effective analytical placer for FPGAs., , and . DAC, page 10:1-10:6. ACM, (2013)