%0 Conference Paper %1 jiao2011analysis %A Jiao, Jiajia %A Fu, Yuzhuo %A Jiang, Jiang %B NORCHIP, 2011 %D 2011 %K analysis evaluation noc reliability %P 1-4 %R 10.1109/NORCHP.2011.6126730 %T Architecture-level analysis and evaluation of transient errors on NoC %U http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6126730&navigation=1 %X Scaling IC technology, lower voltage supply and high frequency etc cause transient errors to dominate in VLSI reliability design. NoC, as the most promising communication infrastructure for many-core system, also faces bits upset challenge due to transient errors. In this paper, we focus on analysis and evaluation of transient errors on NoC from architecture perspective: 1) classify the transient errors in NoC and analyse the cross-relationship between different types of errors to explore fine grain transient errors effect; 2) define the unified architecture-level metrics for evaluating transient errors effect on performance and reliability to guide fault tolerance methods selection; 3) do some cases study about transient errors in NoC based on accurate simulation results to validate our approach.

@inproceedings{jiao2011analysis, abstract = {Scaling IC technology, lower voltage supply and high frequency etc cause transient errors to dominate in VLSI reliability design. NoC, as the most promising communication infrastructure for many-core system, also faces bits upset challenge due to transient errors. In this paper, we focus on analysis and evaluation of transient errors on NoC from architecture perspective: 1) classify the transient errors in NoC and analyse the cross-relationship between different types of errors to explore fine grain transient errors effect; 2) define the unified architecture-level metrics for evaluating transient errors effect on performance and reliability to guide fault tolerance methods selection; 3) do some cases study about transient errors in NoC based on accurate simulation results to validate our approach.}, added-at = {2013-09-26T16:34:40.000+0200}, author = {Jiao, Jiajia and Fu, Yuzhuo and Jiang, Jiang}, biburl = {https://www.bibsonomy.org/bibtex/2a534dbb8993406f5a58cb518315ca2c5/eberle18}, booktitle = {NORCHIP, 2011}, description = {IEEE Xplore - Architecture-level analysis and evaluation of transient errors on NoC}, doi = {10.1109/NORCHP.2011.6126730}, interhash = {b5f7fe98149cbbd9fd72e4fd831b1fd4}, intrahash = {a534dbb8993406f5a58cb518315ca2c5}, keywords = {analysis evaluation noc reliability}, pages = {1-4}, timestamp = {2013-09-26T16:34:40.000+0200}, title = {Architecture-level analysis and evaluation of transient errors on NoC}, url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6126730&navigation=1}, year = 2011 }