%0 Journal Article %1 journals/jssc/ArimotoMHDSI07 %A Arimoto, Kazutami %A Morishita, Fukashi %A Hayashi, Isamu %A Dosaka, Katsumi %A Shimano, Hiroki %A Ipposhi, Takashi %D 2007 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 2611-2619 %T A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. %U http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#ArimotoMHDSI07 %V 42

@article{journals/jssc/ArimotoMHDSI07, added-at = {2023-06-26T00:00:00.000+0200}, author = {Arimoto, Kazutami and Morishita, Fukashi and Hayashi, Isamu and Dosaka, Katsumi and Shimano, Hiroki and Ipposhi, Takashi}, biburl = {https://www.bibsonomy.org/bibtex/2d3b7cfa965318d6f0c337e64a1c6b61a/dblp}, ee = {https://doi.org/10.1109/JSSC.2007.907185}, interhash = {6b019b6b4e49c543ca975e754b1d81f3}, intrahash = {d3b7cfa965318d6f0c337e64a1c6b61a}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {2611-2619}, timestamp = {2024-04-08T10:44:22.000+0200}, title = {A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#ArimotoMHDSI07}, volume = 42, year = 2007 }