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Disambiguation of "Shimano, Hiroki"

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A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs.

, , , , , and . IEEE J. Solid State Circuits, 42 (11): 2611-2619 (2007)

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Hiroki Takahashi

Hiroki Kawamura

Takuji Shimano

Hiroki Sumizawa

 

Other publications of authors with the same name

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform., , , and . IEICE Trans. Electron., 90-C (10): 1927-1935 (2007)A 1-V 46-ns 16-Mb SOI-DRAM with body control technique., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 32 (11): 1712-1720 (1997)A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 31 (11): 1645-1655 (1996)A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM., , , , , , , , , and . ITC, page 319-324. IEEE Computer Society, (1996)A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs., , , , , and . IEEE J. Solid State Circuits, 42 (11): 2611-2619 (2007)A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 853-861 (2007)On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform., , , and . IEICE Trans. Electron., 92-C (3): 356-363 (2009)