%0 Journal Article %1 journals/jssc/YehK10 %A Yeh, Chih-Ting %A Ker, Ming-Dou %D 2010 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 2476-2486 %T Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. %U http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#YehK10 %V 45

@article{journals/jssc/YehK10, added-at = {2020-08-30T00:00:00.000+0200}, author = {Yeh, Chih-Ting and Ker, Ming-Dou}, biburl = {https://www.bibsonomy.org/bibtex/2e1024ada04d86361b1ef4c3a1263836f/dblp}, ee = {https://doi.org/10.1109/JSSC.2010.2075370}, interhash = {83d64e4f5b50b8483304c63452e55714}, intrahash = {e1024ada04d86361b1ef4c3a1263836f}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {2476-2486}, timestamp = {2020-08-31T11:42:30.000+0200}, title = {Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#YehK10}, volume = 45, year = 2010 }