%0 Conference Paper %1 conf/apccas/NairEJ08 %A Nair, Pradeep S. %A Eratne, Savithra %A John, Eugene %B APCCAS %D 2008 %I IEEE %K dblp %P 972-975 %T Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm. %U http://dblp.uni-trier.de/db/conf/apccas/apccas2008.html#NairEJ08 %@ 978-1-4244-2342-2

@inproceedings{conf/apccas/NairEJ08, added-at = {2021-10-14T00:00:00.000+0200}, author = {Nair, Pradeep S. and Eratne, Savithra and John, Eugene}, biburl = {https://www.bibsonomy.org/bibtex/2e298027f1c9d2e0ad0d73eccf60822be/dblp}, booktitle = {APCCAS}, crossref = {conf/apccas/2008}, ee = {https://doi.org/10.1109/APCCAS.2008.4746186}, interhash = {15a32763834f6f34cee8ce970dd3517b}, intrahash = {e298027f1c9d2e0ad0d73eccf60822be}, isbn = {978-1-4244-2342-2}, keywords = {dblp}, pages = {972-975}, publisher = {IEEE}, timestamp = {2024-04-10T05:03:23.000+0200}, title = {Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm.}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2008.html#NairEJ08}, year = 2008 }