In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Description
IEEE Xplore - Analysis of error recovery schemes for networks on chips
%0 Journal Article
%1 murali2005analysis
%A Murali, S.
%A Theocharides, T.
%A Vijaykrishnan, N.
%A Irwin, M.J.
%A Benini, L.
%A De Micheli, G.
%D 2005
%J Design Test of Computers, IEEE
%K analysis noc overview recovery
%N 5
%P 434-442
%R 10.1109/MDT.2005.104
%T Analysis of error recovery schemes for networks on chips
%U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1511975&tag=1
%V 22
%X In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
@article{murali2005analysis,
abstract = {In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.},
added-at = {2013-04-17T18:09:28.000+0200},
author = {Murali, S. and Theocharides, T. and Vijaykrishnan, N. and Irwin, M.J. and Benini, L. and De Micheli, G.},
biburl = {https://www.bibsonomy.org/bibtex/2ef96f2abc96ea06cd45152682d51b9e1/eberle18},
description = {IEEE Xplore - Analysis of error recovery schemes for networks on chips},
doi = {10.1109/MDT.2005.104},
interhash = {6ad514d7a1c39e4f3aec2c29d4943cce},
intrahash = {ef96f2abc96ea06cd45152682d51b9e1},
issn = {0740-7475},
journal = {Design Test of Computers, IEEE},
keywords = {analysis noc overview recovery},
number = 5,
pages = {434-442},
timestamp = {2013-04-17T18:09:28.000+0200},
title = {Analysis of error recovery schemes for networks on chips},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1511975&tag=1},
volume = 22,
year = 2005
}